AMD Instinct MI455X

The AMD Instinct MI455X is a data center GPU accelerator announced by AMD on 23 July 2026 at Advancing AI 2026 in San Francisco. It is the flagship, AI-focused member of the Instinct MI400 series and the compute engine of the AMD Helios rackscale reference design, which packages 72 MI455X GPUs with 18 6th Gen EPYC "Venice" CPUs in a single scale-up domain.^[1][2]

Built on AMD's 5th generation CDNA architecture (CDNA 5), the MI455X pairs 432 GB of HBM4 memory across twelve stacks with a published peak memory bandwidth of 23.3 TB/s and 40.3 PFLOPS of peak OCP MXFP4 matrix throughput. It is the first AMD Instinct generation to use a UALink over Ethernet (UALoE) scale-up fabric in place of Infinity Fabric GPU-to-GPU links, and AMD describes it as designed specifically for Helios, packaged four GPUs to a module rather than as a standalone OAM board.^[3][4][10]

This article covers the MI455X SKU itself. For the MI400 family as a whole, including the MI430X and MI440X variants and AMD's multi-year Instinct roadmap, see AMD Instinct MI400. For the rack that the MI455X ships inside, see AMD Helios rack.

Announcement and availability

AMD first described the MI400 series at Advancing AI 2025 and disclosed the MI455X name at CES in January 2026. The part was formally launched on 23 July 2026, the date AMD lists as the official launch date on the MI455X product page.^[3][1]

AMD's launch materials describe the Helios rackscale solution as "now in production to be deployed by leading AI companies at gigawatt scale." AMD has not separately published a general-availability or volume-shipment date for the MI455X as a discrete component, and the accelerator is not offered as a standalone board: the datasheet states that four liquid-cooled MI455X GPUs are packaged onto a single Enhanced Accelerator Module (EAM), one of which populates a Helios compute tray.^[1][4]

Two other availability statements from AMD are worth separating carefully. OpenAI said it expects to bring Helios online beginning in the fourth quarter of 2026, with deployments accelerating through 2027. Separately, the Helios product page FAQ still stated, as of 27 July 2026, that the reference design "is being shared with partners now, with volume deployments expected in 2H 2026."^[1][5]

Architecture

The MI455X is a multi-chip package built on the 5th generation AMD CDNA architecture. AMD's datasheet lists eight Accelerated Compute Dies (XCDs) and two I/O dies, 256 compute units (called Work Group Processors on the product page), a peak engine clock of 2.4 GHz, and a transistor count of 320 billion. Lithography is given as "TSMC 2nm | 3nm FinFET," reflecting a split where the compute dies use the more advanced node and the I/O and fabric dies use the older one.^[3][4]

On the MI400 series product page AMD describes the package as using stacked 3D hybrid bonded compute dies on high-density interconnects, assembled on an advanced CoWoS-L package. Independent write-ups from the launch, based on AMD's architecture disclosures, add that the 192 MB of global L2 cache is split across two fabric-and-cache dies, that each WGP carries 64 KB of L1 data cache and 320 KB of local data share, and that CDNA 5 moves the ISA to Wave32 execution from the Wave64 model used in earlier CDNA generations. AMD confirms the 192 MB L2 figure on the MI455X specification page and the Wave32 execution model on the MI400 series page, but neither AMD page itemizes the fabric-and-cache dies separately.^[9][3][6][7]

A notable architectural choice is the near-elimination of high-precision floating point. The MI455X is rated at 5 TFLOPS for both matrix and vector FP64, against 78.6 TFLOPS on the previous-generation MI355X. AMD positions the sibling MI430X as the HPC and sovereign AI part, quoting up to 288 TFLOPS of hardware FP64 for that SKU.^[3][8][1]

Specifications

All values below are as published by AMD on the MI455X product page and datasheet. AMD has not published a TDP, typical board power, or die area for the MI455X; the Helios launch blog states that power and thermal figures are available to qualified customers and partners under non-disclosure agreement.^[3][4][2]

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A note on the memory bandwidth figure

AMD's own materials are inconsistent on peak memory bandwidth. The MI455X product specification page, the MI455X datasheet, and the "GPU Advancements" section of the MI400 series page all state 23.3 TB/s. The MI400 series FAQ contradicts itself: the answer to "What makes AMD Instinct MI455X GPUs standout?" gives 19.6 TB/s, while the answer to "What are the proof points of AMD Instinct MI455X GPU?" a few entries later gives 23.3 TB/s. The Helios product page compute-tray description also states 19.6 TB/s. The 23.3 TB/s figure appears in the formal specification tables and in AMD's launch-day comparison charts, and is the value AMD uses when claiming 2.9 times the memory bandwidth of the MI355X (8 TB/s), so it should be treated as the authoritative number; the 19.6 TB/s figure appears to be a stale pre-launch specification that AMD has not removed from all pages.^[3][4][9][5]

Comparison with the previous generation

Against the CDNA 4 Instinct MI355X, which launched on 12 June 2025, the MI455X delivers roughly four times the peak low-precision matrix throughput, 1.5 times the memory capacity, and 2.9 times the memory bandwidth, while cutting FP64 throughput by more than an order of magnitude.^[8][3][4]

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AMD's own generational claims are footnoted as MI400-006 (up to 4 times the previous-generation performance on 4-bit and 8-bit matrix floating point) and MI400-008 (up to 2.9 times higher peak memory bandwidth), both calculated from published peak theoretical specifications rather than measured.^[4][2]

The "34x token throughput" claim

AMD's launch press release states that "AMD Instinct MI455X GPUs deliver 34x higher token throughput compared to MI355X GPUs." This is a vendor marketing comparison, not an independently verified benchmark, and the published test configuration is only partially disclosed. The full footnote, numbered MI400-020, reads:

Based on measurements and calculations by AMD Performance Labs in July 2026, for the AMD Instinct MI455X GPU to determine measured token throughput at high, medium and low interactivity points run on Deepseek V4 Flash with FP4 serving compared to AMD Instinct MI355X GPU. System manufacturers may vary configurations, yielding different results.^[1]

AMD's Helios launch blog is more specific about which operating point produces the headline number: on DeepSeek-V4-Flash, MI455X GPUs deliver "up to 34X higher token throughput at high interactivity and up to 18X lower token cost" than MI355X GPUs. The 34x figure is therefore the best case at the high-interactivity end of the curve, where per-user token rate is highest and batch sizes are smallest, and not a flat generational multiplier across serving regimes.^[2]

What AMD has not published is equally important. The footnote does not state how many GPUs were used on either side of the comparison, what tensor or expert parallelism configuration was used, what numeric precision the MI355X baseline ran, what serving stack and versions were used, or what the throughput numbers were in absolute terms. AMD's general disclaimer on the same blog adds that "performance measurements were obtained on pre-production or reference hardware."^[2]

For context on the size of the gap, AMD's own published peak specifications imply about 4 times the MXFP4 matrix throughput, 1.5 times the memory capacity, and 2.9 times the memory bandwidth per GPU relative to the MI355X. A 34x result is therefore not explicable by per-GPU arithmetic throughput alone, and would have to come predominantly from system-level effects that AMD did not itemize, such as the difference between a 72-GPU single scale-up domain and an 8-GPU MI355X node, larger resident KV cache, and serving-software gains. Readers should treat 34x as a best-case, AMD-measured, system-dependent figure rather than a per-GPU generational speedup.^[3][8][2]

Position in the MI400 series

At CES in January 2026, AMD described three MI400 variants: the MI455X for frontier AI training and inference, the MI430X for HPC and sovereign AI with full FP64 support, and the MI440X for on-premises enterprise servers pairing eight GPUs with a single EPYC "Venice" CPU. As of 27 July 2026, AMD's Advancing AI 2026 launch materials and product pages cover the MI455X and MI430X but do not mention the MI440X, and no AMD product page for the MI440X exists; the MI440X therefore remains a disclosed but unlaunched part.^[10][1][9]

Alongside the MI400 series, AMD's launch press release also promoted the CDNA 4 based Instinct MI350P, a drop-in PCIe accelerator for existing infrastructure rather than a rack-scale part. Despite the release's "AMD also launched" wording, the MI350P was not new at Advancing AI 2026: AMD had announced it on 7 May 2026, and it already appeared as supported hardware in the ROCm 7.14.0 compatibility matrix dated 16 July 2026, a week before the event.^[1][15][14]

Role in Helios rackscale systems

The MI455X is designed specifically for Helios, AMD's first rack-scale reference design and the first full rack built on Meta's Open Rack Wide (ORW) standard submitted to the Open Compute Project. A Helios rack holds 18 compute trays, each with one EAM carrying four MI455X GPUs attached over Infinity Fabric to a 6th Gen EPYC "Venice" CPU, for 72 GPUs and 18 CPUs per rack.^[4][5]

At rack level AMD quotes 2.9 exaFLOPS of peak OCP MXFP4 compute, 1.4 exaFLOPS of FP8, 31 TB of HBM4, 1.7 PB/s of aggregate memory bandwidth, 260 TB/s of aggregate scale-up bandwidth and 43 TB/s of scale-out bandwidth. Scale-up runs over four UALoE cartridges providing all-to-all connectivity across the 72 GPUs in a single load/store domain with automatic link failover; scale-out uses standards-based Ethernet aligned with the Ultra Ethernet Consortium, driven by AMD Pensando "Vulcano" 800 Gbps AI NICs. Helios is a reference design licensed to OEM and ODM partners rather than a product AMD sells directly, with systems expected from Bull, HPE, Lenovo, Supermicro, Sanmina and Wiwynn.^[5][9][4][1]

The MI455X supports subdividing a Helios rack into virtual pods ranging from four GPUs sharing a compute tray up to the full rack, with GPU-level compute partitioning, four spatial memory partitions exposed as isolated NUMA regions, and SR-IOV.^[4]

Competitive position

AMD positions the MI455X directly against NVIDIA's Vera Rubin generation. Every cross-vendor number below is a vendor claim. As of 27 July 2026 no independent third-party benchmarks of the MI455X had been published, and no MLPerf submission using MI455X existed; AMD's most recent MLPerf Inference results, from v6.0, used MI355X GPUs.^[11][12]

AMD's published per-GPU comparison chart puts the MI455X at 40 PFLOPS of peak OCP MXFP4 against 35 PFLOPS of dense NVFP4 for the Rubin GPU, 20 against 18 PFLOPS at FP8/FP6, 5 against 4 PFLOPS at FP16/BF16, 432 GB against 288 GB of memory, and 23.3 against 22.0 TB/s of memory bandwidth. AMD's footnote MI400-003 states that the NVIDIA figures come from "published preliminary specifications." At rack level, AMD claims Helios delivers up to 15 percent more AI compute, 50 percent more HBM capacity and 50 percent more scale-out bandwidth than an NVIDIA Vera Rubin NVL72, and up to 30 percent more tokens per dollar, the last calculated from a modeled Kimi K2 Thinking workload at 32K input and 8K output with projected hourly GPU pricing (footnote MI400-025).^[9][2][1]

Several caveats apply to those comparisons. AMD's dense-versus-dense FP4 comparison is like-for-like, but NVIDIA separately claims up to 50 PFLOPS of NVFP4 for inference on Rubin using third-generation Transformer Engine adaptive compression, which AMD's chart does not address. NVIDIA's published Rubin specifications are 288 GB of HBM4 per GPU at up to 22 TB/s, 336 billion transistors, 224 streaming multiprocessors, 3.6 TB/s of bidirectional NVLink 6 scale-up bandwidth per GPU (the same figure AMD quotes for UALoE), and up to 3.6 exaFLOPS of AI inference compute per NVL72 rack. AMD's throughput advantage claims on Kimi K2 Thinking, of 15, 12 and 10 percent per GPU at low, medium and high interactivity, are explicitly described in AMD's own text as modeled rather than measured.^[13][2]

Customers and announced deployments

Named Helios and MI455X commitments announced at or around the launch include:

• Anthropic, which announced a strategic partnership to deploy up to 2 gigawatts of MI455X GPUs in Helios racks, together with a multi-year engineering collaboration to use Claude to optimize workloads for Instinct GPUs and accelerate ROCm development.^[1]
• OpenAI, which is optimizing GPT-class workloads on MI455X and Helios using Triton with ROCm, and expects to bring Helios online beginning in Q4 2026.^[1]
• Oracle Cloud Infrastructure, which AMD's MI455X datasheet says plans to deploy 50,000 MI455X GPUs beginning in 2026.^[4]
• Meta, which is validating 6th Gen EPYC platforms and has begun testing workloads on Helios racks ahead of at-scale deployment.^[1]
• Additional named adopters: Microsoft, HUMAIN, TensorWave, Vultr and Cirrascale.^[1]

AMD's datasheet also states that Instinct GPUs are "trusted by eight of the world's top ten AI organizations," with public commitments to deploy up to six gigawatts of Instinct capacity across multi-year collaborations.^[4]

Software and ROCm support

The MI455X is supported through AMD's ROCm open software stack. AMD's product page lists HIP, OpenMP, OpenCL and ROCm support, and framework support for PyTorch, TensorFlow, JAX, ONNX Runtime, SGLang, Triton, Kokkos and RAJA; Vulkan is listed as unsupported. The MI455X datasheet adds vLLM and DeepSeek to the supported list and names AMD Primus as the distributed training and fine-tuning runtime. Operating system support is listed as Linux x86-64 only.^[3][4]

At Advancing AI 2026 AMD also introduced ROCm.ai, an AI-assisted GPU development platform intended to let coding agents including Claude, Codex and Cursor work natively with AMD platforms; AMD said ROCm.ai is being used to accelerate software enablement for the MI455X, and that PyTorch, Hugging Face, vLLM and SGLang are already enabled on the part.^[1]

One qualification on software readiness: as of 27 July 2026, AMD's public ROCm compatibility matrix, then at version 7.14.0 and dated 16 July 2026, listed supported Instinct hardware only through the MI350 series (gfx950) and did not yet list the MI455X or any MI400 series part. Publicly documented ROCm support for the MI455X therefore lagged the hardware launch.^[14]

See also

• AMD Instinct MI400
• AMD Helios rack
• AMD Instinct MI430X
• AMD Instinct MI350P
• AMD Instinct MI355X
• AMD Instinct MI325X
• AMD Instinct MI300X
• AMD EPYC Venice
• AMD Advancing AI 2026
• NVIDIA Vera Rubin
• DeepSeek V4
• Inference
• KV cache

References

1. "AAI 2026: AMD Delivers Full-Stack Compute for the Agentic AI Era", AMD press release, 23 July 2026. https://ir.amd.com/news-events/press-releases/detail/1294/aai-2026-amd-delivers-full-stack-compute-for-the-agentic-ai-era ↩
2. "AMD Launches Helios: The Highest Performing Rackscale AI Infrastructure Solution", AMD blog, 23 July 2026. https://www.amd.com/en/blogs/2026/amd-launches-helios-the-highest-performing-rackscale-ai-infrastructure-solution.html ↩
3. "AMD Instinct MI455X GPUs", AMD product specification page, accessed 27 July 2026. https://www.amd.com/en/products/accelerators/instinct/mi400/mi455x.html ↩
4. "Datasheet: AMD Instinct MI455X GPU", AMD product brochure LE-93204-000, July 2026. https://www.amd.com/content/dam/amd/en/documents/products/accelerators/instinct/amd-instinct-mi455x_brochure.pdf ↩
5. "AMD Helios Rackscale Solution", AMD product page, accessed 27 July 2026. https://www.amd.com/en/products/rackscale-solutions/helios.html ↩
6. "AMD's Instinct MI455X: Aiming for the Sun", Chips and Cheese, July 2026. https://chipsandcheese.com/p/amds-instinct-mi455x-aiming-for-the ↩
7. "AMD MI455X and Helios: 432GB HBM4, 72-GPU Racks, and a Real Answer to Vera Rubin", StorageReview, July 2026. https://www.storagereview.com/news/amd-mi455x-and-helios-432gb-hbm4-72-gpu-racks-and-a-real-answer-to-vera-rubin ↩
8. "AMD Instinct MI355X GPUs", AMD product specification page, accessed 27 July 2026. https://www.amd.com/en/products/accelerators/instinct/mi350/mi355x.html ↩
9. "AMD Instinct MI400 Series GPUs", AMD product page, accessed 27 July 2026. https://www.amd.com/en/products/accelerators/instinct/mi400.html ↩
10. Anton Shilov, "AMD touts Instinct MI430X, MI440X, and MI455X AI accelerators and Helios rack-scale AI architecture at CES", Tom's Hardware, 6 January 2026. https://www.tomshardware.com/tech-industry/artificial-intelligence/amd-touts-instinct-mi430x-mi440x-and-mi455x-ai-accelerators-and-helios-rack-scale-ai-architecture-at-ces-full-mi400-series-family-fulfills-a-broad-range-of-infrastructure-and-customer-requirements ↩
11. "MLPerf 6.0: AMD Instinct MI355X GPUs Surpass 1M Tokens/Sec, Power New Workloads and Demonstrate Distributed Inference", AMD blog, 2026. https://www.amd.com/en/blogs/2026/amd-delivers-breakthrough-mlperf-inference-6-0-results.html ↩
12. "AMD Instinct MI355X Achieves MLPerf Inference v6.0 Gains with Over 1 Million Tokens per Second", StorageReview, 2026. https://www.storagereview.com/news/amd-instinct-mi355x-achieves-mlperf-inference-v6-0-gains-with-over-1-million-tokens-per-second-and-supports-scalable-rocm-stack ↩
13. "Inside the NVIDIA Vera Rubin Platform: Six New Chips, One AI Supercomputer", NVIDIA Technical Blog, 2026. https://developer.nvidia.com/blog/inside-the-nvidia-rubin-platform-six-new-chips-one-ai-supercomputer/ ↩
14. "ROCm 7.14.0 compatibility matrix", AMD ROCm documentation, dated 16 July 2026, accessed 27 July 2026. https://rocm.docs.amd.com/en/latest/compatibility/compatibility-matrix.html ↩
15. "AMD Instinct MI350P PCIe GPUs: Run Enterprise AI on Your Existing Infrastructure", AMD blog, 7 May 2026. https://www.amd.com/en/blogs/2026/amd-instinct-mi350p-pcie-gpus-run-enterprise-ai-on-your.html ↩